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FM28V100-TG 데이터시트(PDF) 3 Page - Ramtron International Corporation |
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FM28V100-TG 데이터시트(HTML) 3 Page - Ramtron International Corporation |
3 / 13 page FM28V100 - 128Kx8 FRAM Rev. 1.1 Mar. 2009 Page 3 of 13 Functional Truth Table 1 /CE1 CE2 /WE A(16:3) A(2:0) Operation H X X L X X X X X X Standby/Idle ↓ L H ↑ H H V V V V Read L H H No Change Change Page Mode Read L H H Change V Random Read ↓ L H ↑ L L V V V V /CE-Controlled Write 2 L H ↓ V V /WE-Controlled Write 2, 3 L H ↓ No Change V Page Mode Write 4 ↑ L H ↓ X X X X X X Starts Precharge Notes: 1) H=Logic High, L=Logic Low, V=Valid Address, X=Don’t Care. 2) For write cycles, data-in is latched on the rising edge of /CE1 or /WE of the falling edge of CE2, whichever comes first. 3) /WE-controlled write cycle begins as a Read cycle and A(16:3) is latched then. 4) Addresses A(2:0) must remain stable for at least 15 ns during page mode operation. |
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