IDT5V50009

SPREAD SPECTRUM CLOCK GENERATOR

SSCG

IDT™ SPREAD SPECTRUM CLOCK GENERATOR

2

IDT5V50009

REV C 040609

Pin Assignment

Spread Percentage Select Table

0 = connect to GND

1 = connect directly to VDD

* Default has internal pull up resistor to VDD

Pin Descriptions

X1/ICLK

GND

S0

VDD

SSCLK

PD

REFCLK

X2

1

2

3

4

8

7

6

5

8 pi n ( 150 mi l ) SOI C

S0

Spread

Direction

Spread

Percentage (%)

0

Down

-1.25

1

Down

-1.75

Pin

Number

Pin

Name

Pin Type

Pin Description

1

X1/ICLK

Input

Connect to a 20 to 40 MHz crystal or clock.

2

GND

Power

Connect to ground.

3

S0

Input

Select spread percentage per table above. Weak Internal pull-up.

4

SSCLK

Output

Spread spectrum clock output per table above. Weak Internal Pull down

5

REFCLK

Output

CMOS level clock output matches the nominal frequency of the input crystal or clock.

Weak Internal Pull down

6PD

Input

Power down tri-state. This pin powers down entire chip and tri-state the outputs when

low. Weak Internal pull-up.

7

VDD

Power

Connect to 3.3 V.

8

X2

Input

Connect to a 20 to 40 MHz crystal or leave unconnected.