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ADC0801 데이터시트(PDF) 5 Page - National Semiconductor (TI) |
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ADC0801 데이터시트(HTML) 5 Page - National Semiconductor (TI) |
5 / 41 page AC Electrical Characteristics (Continued) Note 7: The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see timing diagrams). Note 8: None of these A/Ds requires a zero adjust (see section 2.5.1). To obtain zero code at other analog input voltages see section 2.5 and Figure 7. Note 9: The VREF/2 pin is the center point of a two-resistor divider connected from VCC to ground. In all versions of the ADC0801, ADC0802, ADC0803, and ADC0805, and in the ADC0804LCJ, each resistor is typically 16 k Ω. In all versions of the ADC0804 except the ADC0804LCJ, each resistor is typically 2.2 kΩ. Note 10: Human body model, 100 pF discharged through a 1.5 k Ω resistor. Typical Performance Characteristics Logic Input Threshold Voltage vs. Supply Voltage DS005671-38 Delay From Falling Edge of RD to Output Data Valid vs. Load Capacitance DS005671-39 CLK IN Schmitt Trip Levels vs. Supply Voltage DS005671-40 f CLK vs. Clock Capacitor DS005671-41 Full-Scale Error vs Conversion Time DS005671-42 Effect of Unadjusted Offset Error vs. V REF/2 Voltage DS005671-43 Output Current vs Temperature DS005671-44 Power Supply Current vs Temperature (Note 9) DS005671-45 Linearity Error at Low V REF/2 Voltages DS005671-46 www.national.com 5 |
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