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AZOLED043A-T 데이터시트(PDF) 11 Page - AZ Displays |
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AZOLED043A-T 데이터시트(HTML) 11 Page - AZ Displays |
11 / 25 page VDC_ENB=1, VDDD is input. (Input range = 1.6V~2.75V) 32 VCC P A power supply for the Digital circuit. (1.5V~3.6V) 33 VSSD P Digital ground pin. It must connect to external ground. 34 NRESET I Reset pin. Setting either pin low initializes the LSI. Must be reset after power is supplied. (Normally pull high) 35 NCS I Serial Interface chip enable pin. (Normally pull high) 36 SCL I Serial Interface clock input pin. (Normally pull high) 37 SDA I Serial Interface data line. (Normally pull high) 38 DE I Data enable: When VSYNC+HSYNC+DE mode, DE=H: Data enable, DE=L: Data disable (Black). (Normally pull low) 39 VSYNC I Frame synchronizing signal. If VSPL=0: Active low. If VSPL=1: Active high. 40 HSYNC I Line synchronizing signal. If HSPL=0: Active low. If HSPL=1: Active high. 41 DCLK I Dot clock signal. If DPL=0: Data are input on the rising edge of DOTCLK. If DPL=1: Data are input on the falling edge of DOTCLK. 42 D27 43 D26 44 D25 45 D24 46 D23 47 D22 48 D21 49 D20 50 D17 51 D16 52 D15 53 D14 54 D13 55 D12 56 D11 57 D10 58 D07 59 D06 60 D05 61 D04 62 D03 63 D02 I Digital data input. DX0 is LSB and DX7 is MSB. (Normally pull low) 1. If parallel RGB input mode is used, D0X, D1X, and D2X indicate R, G, and B data in turn. 2. If serial RGB or RGBD or CCIR601 or CCIR656 input mode is selected, only D07~D00 are used, and others short to GND. DX7~DX0 has 8-bit width, respectively to compose 16,777,216 color and 256 gray scale of 1 pixel. AZ DISPLAYS, INC. PAGE 11 OF 25 |
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