Preliminary Technical Data

AD7291

Rev. PrC | Page 9 of 21

Table 6. Temperature Data Format

Temperature (°C)

Digital Output

−40

1111 0110 0000

−25

1111 1001 1100

−10

1111 1101 1000

−0.25

1111 1111 1111

0

0000 0000 0000

+0.25

0000 0000 0001

+10

0000 0010 1000

+25

0000 0110 0100

+50

0000 1100 1000

+75

0001 0010 1100

+100

0001 1001 0000

+105

0001 1010 0100

+125

0001 1111 0100

Temperature Conversion Formula:

Positive Temperature = ADC Code/4

Negative Temperature = (4096 - ADC Code)/4

to easily interface to both a 1.8V and 3V processors. For

of 3.3V while still being able to interface to 1.8V processors.

0.3V (see the Maximum Ratings Section).

THE REFERENCE

The AD7291 can operate with either the internal 2.5V on-chip

reference or an externally applied reference. The EXT_REF bit

in the Command Register is used to determine whether the

internal reference is used. If the EXT_REF bit is selected in the

command register, an external reference can be supplied

enabled. Suitable external reference sources for the AD7291

include AD780, AD1582, ADR431, REF193, and ADR391.

The internal reference circuitry consists of a 2.5V band-gap

reference and a reference buffer. When the AD7291 is operated

in internal reference mode, the 2.5V internal reference is avail-

10 μF capacitor. It is recommended that the internal reference be

buffered before applying it elsewhere in the system. The internal

reference is capable of sourcing up to TBD μA of current when

the converter is static. The reference buffer requires 10ms to

power up and charge the TBD μF decoupling capacitor during

the power-up time.

RESET

The AD7291 includes a reset feature, which can be used to reset

the device and the content of all internal registers including the

control register to their default state. To activate the reset

operation, the PD pin should be brought low for a minimum of

TBD ns and a maximum of 100ns and is asynchronous to the

clock, hence it can be triggered at any time. If the PD pin is held

low for greater than 100ns the part will enter full power-down

mode. It is imperative that the PD pin be held at a stable logic

level at all times to ensure normal operation.