전자부품 데이터시트 검색엔진 |
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AZP92 데이터시트(PDF) 1 Page - Arizona Microtek, Inc |
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AZP92 데이터시트(HTML) 1 Page - Arizona Microtek, Inc |
1 / 9 page AZP92 ECL/PECL ÷1, ÷2 Clock Generation Chip with Selectable Enable 1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (623) 505-2414 www.azmicrotek.com ARIZONA MICROTEK, INC. FEATURES • Green and RoHS Compliant / Lead (Pb) Free Package Available • 3.0V to 5.5V Operation • Selectable Divide Ratio • Selectable Enable Polarity and Threshold (CMOS/TTL or PECL) • Selectable Input Biasing • High Bandwidth for ≥1GHz • -147 dBc/Hz (÷1), -150 dBc/Hz (÷2) Typical Noise Floor • Available in a MLP 8 (2x2) Package • S Parameter and IBIS Model Files Available on Arizona Microtek Website DESCRIPTION The AZP92 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function. The divide ratio is selected with the DIV-SEL pin/pad. When DIV-SEL is open (NC), the AZP92 functions as a standard receiver. If DIV-SEL is connected to VEE, it functions as a ÷2 divider. A selectable enable is provided which also functions as a reset when the ÷2 mode is selected. Enable (EN) functionality is selected with the EN-SEL pin/pad which has three valid states: open (NC), VEE, or connected to VEE via a 20k Ω resistor. Leaving EN-SEL open or connecting it to VEE will select the EN pin/pad to function as an active high CMOS/TTL enable. When EN-SEL is open, an internal 75k Ω pull-up resistor is selected which enables the outputs whenever EN is left open. When EN-SEL is connected to VEE, an internal 75kΩ pull-down resistor is selected which disables the outputs whenever EN is left open. Connecting the EN-SEL to VEE with a 20kΩ resistor will select the EN pin/pad to function as an active low PECL/ECL enable with an internal 75k Ω pull-down resistor. In this mode, outputs are enabled when EN is left open (NC). This default logic condition can be overridden by connecting the EN to VCC with an external resistor of ≤20kΩ. Refer to the enable truth table on the next page for detailed operation. MLP 8, 2x2 mm Package (AZP92NA) The AZP92NA provides a VBB with an 1880Ω internal bias resistor from D to VBB. This feature allows AC coupling with minimal external components. The VBB pin supports 1.5mA sink/source current and should be bypassed to ground or VCC with a 0.01 μF capacitor. NOTE: The specifications in the ECL/PECL tables are valid when thermal equilibrium has been established. PACKAGE AVAILABILITY PACKAGE PART NO. MARKING NOTES MLP 8 (2x2) Green / RoHS Compliant / Lead (Pb) Free AZP92NAG P1G <Date Code> 1,2 1 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape & Reel. 2 Date code format: “Y” for year followed by “WW” for week. |
유사한 부품 번호 - AZP92_09 |
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유사한 설명 - AZP92_09 |
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