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TDA8024 데이터시트(PDF) 8 Page - NXP Semiconductors

부품명 TDA8024
상세설명  IC card interface
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제조업체  NXP [NXP Semiconductors]
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TDA8024 데이터시트(HTML) 8 Page - NXP Semiconductors

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2004 July 12
8
Philips Semiconductors
Product specification
IC card interface
TDA8024
8
FUNCTIONAL DESCRIPTION
Throughout this document it is assumed that the reader is
familiar with ISO7816 terminology.
8.1
Power supply
The supply pins for the IC are VDD and GND. VDD should
be in the range of 2.7 to 6.5 V. All signals interfacing with
the system controller are referred to VDD, therefore VDD
should also supply the system controller. All card reader
contacts remain inactive during power-on or power-off.
The internal circuits are maintained in the reset state until
VDD reaches Vth2 +Vhys2 and for the duration of the
internal Power-on reset pulse, tW (see Fig.5). When VDD
falls below Vth2, an automatic deactivation of the contacts
is performed.
A DC/DC converter is incorporated to generate the
5 or 3 V card supply voltage (VCC). The DC/DC converter
should be supplied separately by VDDP and PGND. Due to
the possibility of large transient currents, the two 100 nF
capacitors of the DC/DC converter should be located as
near as possible to the IC and have an ESR less than
100 m
Ω.
The DC/DC converter functions as a voltage doubler or a
voltage follower according to the respective values of VCC
and VDDP (both have thresholds with a hysteresis of
100 mV).
The DC/DC converter function changes as follows:
• VCC = 5 V and VDDP > 5.8 V; voltage follower
• VCC = 5 V and VDDP < 5.7 V; voltage doubler
• VCC = 3 V and VDDP > 4.1 V; voltage follower
• VCC = 3 V and VDDP < 4.0 V; voltage doubler.
Supply voltages VDD and VDDP may be applied to the IC in
any sequence.
After powering the device, OFF remains LOW until
CMDVCC is set HIGH.
During power off, OFF falls LOW when VDD is below the
falling threshold voltage.
8.2
Voltage supervisor
8.2.1
WITHOUT EXTERNAL DIVIDER ON PIN PORADJ
(OR WITH TDA8024AT)
The voltage supervisor surveys the VDD supply. A defined
reset pulse of approximately 8 ms (tW) is used internally to
keep the IC inactive during power-on or power-off of the
VDD supply (see Fig.5).
As long as VDD is less than Vth2 +Vhys2, the IC remains
inactive whatever the levels on the command lines. This
state also lasts for the duration of tW after VDD has reached
a level higher than Vth2 +Vhys2.
When VDD falls below Vth2, a deactivation sequence of the
contacts is performed.
handbook, full pagewidth
Vth2 + Vhys2
VDD
Vth2
ALARM
(internal signal)
supply dropout
power-off
power-on
MDB053
tw
tw
Fig.5 Voltage supervisor.


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