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DM9003 데이터시트(PDF) 24 Page - Davicom Semiconductor, Inc. |
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DM9003 데이터시트(HTML) 24 Page - Davicom Semiconductor, Inc. |
24 / 65 page DM9003 2-port Switch with Processor Interface 24 Preliminary datasheet DM9003-15-DS-P05 April 9, 2009 6.31 Per Port Status Data Register (62H) Bit Name Default Description 7:6 RESERVED P0,RO Reserved 5 LP_FCS P0,RO Link Partner Flow Control Enable Status 4 BIST P0,RO BIST status 1: SRAM BIST fail 0: SRAM BIST pass 3 RESERVED 0,RO Reserved 2 SPEED2 P0,RO PHY Speed Status 0: 10Mbps, 1: 100Mbps 1 FDX2 P0,RO PHY Duplex Status 0: half-duplex, 1: full-duplex 0 LINK2 P0,RO PHY Link Status 0: link fail, 1: link OK 6.32 Per Port Forward Control Register (65H) Bit Name Default Description 7 LOOPBACK PH0,RW Loop-Back Mode The received packet will be forward to this port itself. 6 MONI_TX PH0,RW TX Packet Monitored The transmitted packets are also forward to sniffer port. 5 MONI_RX PH0,RW RX Packet Monitored The received packets are also forward to sniffer port. 4 DIS_BMP PH0,RW Broad/Multicast Not Monitored The received broadcast or multicast packets are not forward to sniffer port. 3 Reserved PH0,RW Reserved 2 TX_DIS PH0,RW Packet Transmit Disabled All packets can not be forward to this port. 1 RX_DIS PH0,RW Packet receive Disabled All received packets are discarded. 0 ADR_DIS PH0,RW Address Learning Disabled The Source Address (SA) field of packet is not learned to address table. |
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