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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DM9008AEP 데이터시트(PDF) 38 Page - Davicom Semiconductor, Inc. |
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DM9008AEP 데이터시트(HTML) 38 Page - Davicom Semiconductor, Inc. |
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38 / 50 page  DM9008AEP Ethernet Controller with General Processor Interface Preliminary 38 Version: DM9008AEP-DS-P03 Dec. 14, 2006 9. Functional Description 9.1 Host Interface The host interface is a general processor local bus that using chip select (pin CS#) to access DM9008A. Pin CS# is default low active which can be re-defined by EEPROM setting. There are only two addressing ports through the access of the host interface. One port is the INDEX port and the other is the DATA port. The INDEX port is decoded by the pin CMD =0 and the DATA port by the pin CMD =1. The contents of the INDEX port are the register address of the DATA port. Before the access of any register, the address of the register must be saved in the INDEX port. 9.2 Direct Memory Access Control The DM9008A provides DMA capability to simplify the access of the internal memory. After the programming of the starting address of the internal memory and then issuing a dummy read/write command to load the current data to internal data buffer, the desired location of the internal memory can be accessed by the read/write command registers. The memory’s address will be increased with the size that equals to the current operation mode (i.e. the 8-bit or 16-bit mode) and the data of the next location will be loaded into internal data buffer automatically. It is noted that the data of the first access (the dummy read/write command) in a sequential burst should be ignored because that the data was the contents of the last read/write command. The internal memory size is 16K bytes. The first location of 3K bytes is used for the data buffer of the packet transmission. The other 13K bytes are used for the buffer of the receiving packets. So in the write memory operation, when the bit 7 of IMR is set, the memory address increment will wrap to location 0 if the end of address (i.e. 3K) is reached. In a similar way, in the read memory operation, when the bit 7 of IMR is set, the memory address increment will wrap to location 0x0C00 if the end of address (i.e. 16K) is reached. 9.3 Packet Transmission There are two packets, sequentially named as index I and index II, can be stored in the TX SRAM at the same time. The index register 02h controls the insertion of CRC and pads. Their statuses are recorded at index registers 03h and 04h respectively. The start address of transmission is 00h and the current packet is index I after software or hardware reset. Firstly write data to the TX SRAM using the DMA port and then write the byte count to byte_ count register at index register 0fch and 0fdh. Set the bit 1 of control register. The DM9008A starts to transmit the index I packet. Before the transmission of the index I packet ends, the data of the next (index II) packet can be moved to TX SRAM. After the index I packet ends the transmission, write the byte count data of the index II to BYTE_COUNT register and then set the bit 1 of control register to transmit the index II packet. The following packets, named index I, II, I, II,…, use the same way to be transmitted. 9.4 Packet Reception The RX SRAM is a ring data structure. The start address of RX SRAM is 0C00h after software or hardware reset. Each packet has a 4-byte header followed with the data of the reception packet which CRC field is included. The format of the 4-byte header is 01h, status, BYTE_COUNT low, and BYTE_COUNT high. It is noted that the start address of each packet is in the proper address boundary which depends on the operation mode (the 8-bit or 16-bit ). |
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