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DM9008AEP ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 28 Page - Davicom Semiconductor, Inc.

๋ถ€ํ’ˆ๋ช… DM9008AEP
์ƒ์„ธ๋‚ด์šฉ  Ethernet Controller with General Processor Interface
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์ œ์กฐ์‚ฌ  DAVICOM [Davicom Semiconductor, Inc.]
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DM9008AEP ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 28 Page - Davicom Semiconductor, Inc.

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DM9008AEP
Ethernet Controller with General Processor Interface
Preliminary
28
Version: DM9008AEP-DS-P03
Dec. 14, 2006
returning a value of one until the reset process is completed
0.14
Loopback
0, RW
Loopback
Loop-back control register
1 = Loop-back enabled
0 = Normal operation
0.13
Speed selection
1, RW
Speed Select
1 = 100Mbps
0 = 10Mbps
Link speed may be selected either by this bit or by
auto-negotiation. When auto-negotiation is enabled and bit 12
is set, this bit will return auto-negotiation selected medium
type
0.12
Auto-negotiatio
n enable
1, RW
Auto-negotiation Enable
1 = Auto-negotiation is enabled, bit 8 and 13 will be in
auto-negotiation status
0.11
Power down
0, RW
Power Down
While in the power-down state, the PHY should respond to
management transactions. During the transition to
power-down state and while in the power-down state, the
PHY should not generate spurious signals on the MII
1=Power down
0=Normal operation
0.10
Isolate
0,RW
Isolate
Force to 0 in application.
0.9
Restart
Auto-negotiation
0,RW/SC Restart Auto-negotiation
1 = Restart auto-negotiation. Re-initiates the auto-negotiation
process. When auto-negotiation is disabled (bit 12 of this
register cleared), this bit has no function and it should be
cleared. This bit is self-clearing and it will keep returning to a
value of 1 until auto-negotiation is initiated by the DM9008A.
The operation of the auto-negotiation process will not be
affected by the management entity that clears this bit
0 = Normal operation
0.8
Duplex mode
1,RW
Duplex Mode
1 = Full duplex operation. Duplex selection is allowed when
Auto-negotiation is disabled (bit 12 of this register is cleared).
With auto-negotiation enabled, this bit reflects the duplex
capability selected by auto-negotiation
0 = Normal operation
0.7
Collision test
0,RW
Collision Test
1 = Collision test enabled. When set, this bit will cause the
COL signal to be asserted in response to the assertion of
TX_EN in internal MII interface.


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