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TDA9950TT 데이터시트(PDF) 5 Page - NXP Semiconductors

부품명 TDA9950TT
상세설명  CEC/I2C-bus translator
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TDA9950_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 22 October 2009
5 of 22
NXP Semiconductors
TDA9950
CEC/I2C-bus translator
In case of independent CEC, a system could have up to four TDA9950 devices on the
same I2C-bus.
The four addresses are defined by the state of the inputs A0 and A1 (logic 1 when
connected to VDD, logic 0 when connected to GND).
8.2 Configuring the TDA9950
The TDA9950 is controlled via a series of registers.
The first byte of any I2C-bus write frame configures the address pointer register APR,
which determines the first TDA9950 register that will be read or written in the remainder of
the I2C-bus transfer. If a read is carried out without a prior write to the address pointer
register, the register returned will be that to which the address pointer register was last
set.
The address pointer auto-increments after a successful read or write for all address
pointer values other than 00h. Auto-incremented addresses above 19h are invalid and
ignored.
Registers 01h to 06h are used for configuration of the TDA9950, whilst repeated
auto-incremented reads starting at register 07h are used to transfer CEC data. Setting the
address pointer register higher than 07h is treated as setting it to 07h, as all message
data transfers must start from register 07h and continue by auto-incrementing in one
contiguous transfer. Transfers via the data registers are formatted using the data register
protocol described in Section 8.5.
8.3 Use of the INT line
As the TDA9950 is an I2C-bus slave device, it provides an additional I/O line to signal to
the host that data is available for reading. This is the INT output line, which should be
monitored by the host. An additional TDA9950 input, on pin INT_POL, allows
configuration of the polarity of operation of the INT line. When the INT line is active, it will
match the state of the input on pin INT_POL.
The state of the INT line is always reflected in the TDA9950 Status Register, so it is
possible to regularly poll this register instead of monitoring the INT line. However, this
method is less efficient and not recommended. The INT indication in the TDA9950 Status
Register is not affected by the setting of the INT polarity input on pin INT_POL.
Table 5.
I2C-bus register configuration
Register
Description
Address
Read/Write
APR
Address Pointer Register
00h
W
CSR
TDA9950 Status Register
00h
R
CER
TDA9950 Error Register
01h
R
CVR
TDA9950 Version Register
02h
R
CCR
TDA9950 Control Register
03h
R/W
ACKH
CEC Address ACK High register
04h
R/W
ACKL
CEC Address ACK Low register
05h
R/W
CCONR
CEC Configuration Register
06h
R/W
CDR
CEC Data Registers
07h - 19h
R/W


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