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74ABT544DB 데이터시트(PDF) 8 Page - NXP Semiconductors |
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74ABT544DB 데이터시트(HTML) 8 Page - NXP Semiconductors |
8 / 15 page 74ABT544_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 15 January 2009 8 of 15 NXP Semiconductors 74ABT544 Octal latched transceiver with dual enable; inverting; 3-state VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Propagation delay latch enable (LEAB, LEBA) to output (An, Bn) 001aac761 VOL VOH VI VM VM tPLH tPHL VM VM GND LEBA, LEAB An, Bn VM = 1.5 V VOH is a typical voltage output level that occurs with the output load. Fig 7. Propagation delay 3-state output enable to HIGH-level and output disable from HIGH-level 001aae907 VM VM VOH − 0.3 V VOH GND VI GND VM tPHZ tPZH An, Bn OEAB, OEBA, EAB, EBA VM = 1.5 V VOL is a typical voltage output level that occurs with the output load. Fig 8. Propagation delay 3-state output enable to LOW-level and output disable from LOW-level 001aae906 VM VM 3.5 V VOL + 0.3 V VM tPLZ tPZL An, Bn OEAB, OEBA, EAB, EBA VOL VI GND |
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