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74AUP1G158GF 데이터시트(PDF) 3 Page - NXP Semiconductors |
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3 / 16 page 74AUP1G158_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 July 2009 3 of 16 NXP Semiconductors 74AUP1G158 Low-power 2-input multiplexer; inverting 6. Pinning information 6.1 Pinning 6.2 Pin description Fig 4. Logic diagram 001aae021 I1 I0 S Y Fig 5. Pin configuration SOT363 (SC-88) Fig 6. Pin configuration SOT886 (XSON6) Fig 7. Pin configuration SOT891 (XSON6) 74AUP1G158 I1 S GND I0 001aae022 1 2 3 6 VCC 5 4 Y 74AUP1G158 GND 001aae023 I1 I0 VCC S Transparent top view 2 3 1 5 4 6 Y 74AUP1G158 GND 001aae024 I1 I0 VCC S Transparent top view 2 3 1 5 4 6 Y Table 3. Pin description Symbol Pin Description I1 1 data input from source 1 GND 2 ground (0 V) I0 3 data input from source 0 Y 4 multiplexer output VCC 5 supply voltage S 6 common data select input |
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