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74AUP1G3208GF 데이터시트(PDF) 9 Page - NXP Semiconductors

부품명 74AUP1G3208GF
상세설명  Low-power 3-input OR-AND gate
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74AUP1G3208GF 데이터시트(HTML) 9 Page - NXP Semiconductors

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74AUP1G3208_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 3 July 2009
9 of 16
NXP Semiconductors
74AUP1G3208
Low-power 3-input OR-AND gate
[1]
All typical values are measured at nominal VCC.
[2]
tpd is the same as tPLH and tPHL.
[3]
All specified values are the average typical values over all stated loads.
[4]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(C
L × VCC
2
× f
o) = sum of the outputs.
12. Waveforms
CL = 5 pF, 10 pF, 15 pF and 30 pF
CPD
power dissipation
capacitance
fi = 1 MHz; VI = GND to VCC
[3][4]
VCC = 0.8 V
-
2.6
-
-
-
-
pF
VCC = 1.1 V to 1.3 V
-
2.7
-
-
-
-
pF
VCC = 1.4 V to 1.6 V
-
2.8
-
-
-
-
pF
VCC = 1.65 V to 1.95 V
-
3.0
-
-
-
-
pF
VCC = 2.3 V to 2.7 V
-
3.5
-
-
-
-
pF
VCC = 3.0 V to 3.6 V
-
4.0
-
-
-
-
pF
Table 9.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
Symbol Parameter
Conditions
25
°C
−40 °C to +125 °C
Unit
Min
Typ[1]
Max
Min
Max
(85
°C)
Max
(125
°C)
Measurement points are given in Table 10.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9.
Input A, B and C to output Y propagation delay times
Y output
A, B, C input
Y output
GND
VI
VOH
VOH
VOL
VOL
VM
VM
VM
VM
VM
VM
tPLH
tPLH
tPHL
tPHL
001aab593


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