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74AUP2GU04 데이터시트(PDF) 2 Page - NXP Semiconductors |
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74AUP2GU04 데이터시트(HTML) 2 Page - NXP Semiconductors |
2 / 16 page 74AUP2GU04_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 3 July 2009 2 of 16 NXP Semiconductors 74AUP2GU04 Low-power dual unbuffered inverter 4. Marking [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 6. Pinning information 6.1 Pinning Table 2. Marking Type number Marking code[1] 74AUP2GU04GW aD 74AUP2GU04GM aD 74AUP2GU04GF aD Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 1A 1Y 1 6 mnb106 2A 2Y 3 4 6 1 1 1 mnb107 4 3 001aad073 540 Ω 50 Ω AY VCC Fig 4. Pin configuration SOT363 (SC-88) Fig 5. Pin configuration SOT886 (XSON6) Fig 6. Pin configuration SOT891 (XSON6) 74AUP2GU04 1A 1Y GND 2A 2Y 001aad699 1 2 3 6 VCC 5 4 74AUP2GU04 GND 001aad700 1A 2A VCC 1Y 2Y Transparent top view 2 3 1 5 4 6 74AUP2GU04 GND 001aad701 1A 2A VCC 1Y 2Y Transparent top view 2 3 1 5 4 6 |
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