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74F543 데이터시트(PDF) 7 Page - NXP Semiconductors |
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74F543 데이터시트(HTML) 7 Page - NXP Semiconductors |
7 / 15 page 74F543_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 26 January 2010 7 of 15 NXP Semiconductors 74F543 Octal latched transceiver with dual enable; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; for test circuit, see Figure 10. Symbol Parameter Conditions 25 °C; V CC = 5.0 V 0 °C to 70 °C; VCC = 5.0 V ± 0.5 V Unit Min Typ Max Min Max tPLH LOW to HIGH propagation delay An to Bn; see Figure 5 3.5 5.5 8.5 3.0 9.0 ns Bn to An; see Figure 5 2.5 4.0 7.0 2.5 7.5 ns LEBA to An; see Figure 6 5.0 7.0 10.0 4.5 11.0 ns LEAB to Bn; see Figure 6 6.0 8.5 11.5 5.5 12.5 ns tPHL HIGH to LOW propagation delay An to Bn; see Figure 5 3.0 5.0 8.0 2.5 8.5 ns Bn to An; see Figure 5 2.5 4.5 7.5 2.5 8.0 ns LEBA to An; see Figure 6 4.0 6.0 9.0 4.0 9.5 ns LEAB to Bn; see Figure 6 4.5 6.5 9.5 4.0 10.0 ns tPZH OFF-state to HIGH propagation delay OEBA to An, OEAB to Bn; see Figure 7 2.0 4.0 7.5 1.5 8.0 ns EBA to An, EAB to Bn; see Figure 7 4.5 7.0 10.5 4.0 11.5 ns tPZL OFF-state to LOW propagation delay OEBA to An, OEAB to Bn; see Figure 8 3.5 5.0 8.5 3.0 9.0 ns EBA to An, EAB to Bn; see Figure 8 5.0 7.0 10.5 4.5 11.0 ns tPHZ HIGH to OFF-state propagation delay OEBA to An, OEAB to Bn; see Figure 7 1.0 3.0 6.5 1.0 7.5 ns EBA to An, EAB to Bn; see Figure 7 2.5 5.0 8.5 2.0 9.5 ns tPLZ LOW to OFF-state propagation delay OEBA to An, OEAB to Bn; see Figure 8 1.5 4.0 7.5 1.0 8.5 ns EBA to An, EAB to Bn; see Figure 8 4.5 7.0 11.0 3.0 12.0 ns tsu(H) set-up time HIGH An to LEAB, Bn to LEBA; see Figure 9 0.0 - - 0.0 - ns An to EAB, Bn to EBA; see Figure 9 1.0 - - 1.5 - ns tsu(L) set-up time LOW An to LEAB, Bn to LEBA; see Figure 9 2.5 - - 3.0 - ns An to EAB, Bn to EBA; see Figure 9 2.5 - - 3.0 - ns th(H) hold time HIGH An to LEAB, Bn to LEBA; see Figure 9 0.0 - - 0.0 - ns An to EAB, Bn to EBA; see Figure 9 0.0 - - 0.0 - ns th(L) hold time LOW An to LEAB, Bn to LEBA; see Figure 9 1.5 - - 2.0 - ns An to EAB, Bn to EBA; see Figure 9 1.5 - - 2.0 - ns tWL pulse width LOW latch enable; see Figure 9 4.0 - - 4.5 - ns |
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