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11 / 21 page 74LVC1G74_8 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 08 — 3 December 2009 11 of 21 NXP Semiconductors 74LVC1G74 Single D-type flip-flop with set and reset; positive edge trigger Measurement points are given in Table 10. VOL and VOH are typical output voltage levels that occur with the output load. Fig 9. The set (SD) and reset (RD) input to output (Q, Q) propagation delays, the set and reset pulse widths and the RD to CP recovery time mnb142 trec tPHL tPHL tW tPLH tPLH VM VM VM tW VM VM VI GND VI GND SD input VI GND RD input CP input VOH VOL Q output VOH VOL Q output trec |
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