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74LVC2G02DP 데이터시트(PDF) 3 Page - NXP Semiconductors |
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74LVC2G02DP 데이터시트(HTML) 3 Page - NXP Semiconductors |
3 / 16 page 74LVC2G02_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 6 June 2008 3 of 16 NXP Semiconductors 74LVC2G02 Dual 2-input NOR gate 6. Pinning information 6.1 Pinning 6.2 Pin description Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig 5. Pin configuration SOT833-1 (XSON8) 74LVC2G02 1A VCC 1B 1Y 2Y 2B GND 2A 001aab642 1 2 3 4 6 5 8 7 74LVC2G02 2B 1Y VCC 2A 2Y 1B 1A GND 001aab643 36 27 18 45 Transparent top view Fig 6. Pin configuration SOT996-2 (XSON8U) Fig 7. Pin configuration XQFN8U 001aai250 74LVC2G02 Transparent top view 8 7 6 5 1 2 3 4 1A 1B 2Y GND VCC 1Y 2B 2A 001aae971 1B 2B 1A 2Y 1Y 2A Transparent top view 3 6 1 5 7 2 terminal 1 index area 74LVC2G02 Table 3. Pin description Symbol Pin Description SOT505-2, SOT765-1, SOT833-1 and SOT996-2 SOT902-1 1A, 2A 1, 5 7, 3 data input 1B, 2B 2, 6 6, 2 data input GND 4 4 ground (0 V) 1Y, 2Y 7, 3 1, 5 data output VCC 8 8 supply voltage |
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