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TMP320C6722BZDHA225 데이터시트(PDF) 9 Page - Texas Instruments

부품명 TMP320C6722BZDHA225
상세설명  Floating-Point Digital Signal Processors
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2.3 CPU Interrupt Assignments
TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720
Floating-Point Digital Signal Processors
www.ti.com
SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008
Table 2-2. New Floating-Point Instructions for C67x+ CPU
FLOATING-POINT
INSTRUCTION
IMPROVES
OPERATION(1)
MPYSPDP
SP x DP
→ DP
Faster than MPYDP.
Improves high Q biquads (bass management) and FFT.
MPYSP2DP
SP x SP
→ DP
Faster than MPYDP.
Improves Long FIRs (EQ).
ADDSP (new to CPU “S” Unit)
SP + SP
→ SP
ADDDP (new to CPU “S” Unit)
DP + DP
→ DP
Now up to four floating-point add and subtract operations in parallel.
Improves FFT performance and symmetric FIR.
SUBSP (new to CPU “S” Unit)
SP – SP
→ SP
SUBDP (new to CPU “S” Unit)
DP – DP
→ DP
(1)
SP means IEEE Single-Precision (32-bit) operations and DP means IEEE Double-Precision (64-bit) operations.
Finally, two new registers, which are dedicated to communication with the dMAX unit, have been added to
the C67x+ CPU. These registers are the dMAX Event Trigger Register (DETR) and the dMAX Event
Status Register (DESR). They allow the CPU and dMAX to communicate without requiring any accesses
to the memory system.
Table 2-3 lists the interrupt channel assignments on the C672x device. If more than one source is listed,
the interrupt channel is shared and an interrupt on this channel could have come from any of the enabled
peripherals on that channel.
The dMAX peripheral has two CPU interrupts dedicated to reporting FIFO status (INT7) and transfer
completion (INT8). In addition, the dMAX can generate interrupts to the CPU on lines INT9–13 and INT15
in response to peripheral events. To enable this functionality, the associated Event Entry within the dMAX
can be programmed so that a CPU interrupt is generated when the peripheral event is received.
Table 2-3. CPU Interrupt Assignments
CPU INTERRUPT
INTERRUPT SOURCE
INT0
RESET
INT1
NMI (From dMAX or EMIF Interrupt)
INT2
Reserved
INT3
Reserved
INT4
RTI Interrupt 0
INT5
RTI Interrupts 1, 2, 3, and RTI Overflow Interrupts 0 and 1.
INT6
UHPI CPU Interrupt (from External Host MCU)
INT7
FIFO status notification from dMAX
INT8
Transfer completion notification from dMAX
INT9
dMAX event (0x2 specified in the dMAX interrupt event entry)
INT10
dMAX event (0x3 specified in the dMAX interrupt event entry)
INT11
dMAX event (0x4 specified in the dMAX interrupt event entry)
INT12
dMAX event (0x5 specified in the dMAX interrupt event entry)
INT13
dMAX event (0x6 specified in the dMAX interrupt event entry)
INT14
I2C0, I2C1, SPI0, SPI1 Interrupts
INT15
dMAX event (0x7 specified in the dMAX interrupt event entry)
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