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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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CS493254 데이터시트(PDF) 10 Page - Cirrus Logic |
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CS493254 데이터시트(HTML) 10 Page - Cirrus Logic |
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10 / 90 page  CS49300 Family DSP 10 DS339F7 1.8. Switching Characteristics — Intel® Host Mode (VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF) Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLKP, in nanoseconds. DCLKP = 1/DCLK. The DSP clock can be defined as follows: External CLKIN Mode: DCLK == CLKIN/4 before and during boot DCLK == CLKIN after boot Internal Clock Mode: DCLK == 10MHz before and during boot, i.e. DCLKP == 100ns DCLK == 65 MHz after boot, i.e. DCLKP == 15.4ns It should be noted that DCLK for the internal clock mode is application specific. The application code users guide should be checked to confirm DCLK for the particular application. 2. This specification is characterized but not production tested. A 470 ohm pull-up resistor was used for characterization to minimize the effects of external bus capacitance. 3. See Tidd from Intel Host Mode in Table 6 on page 46 Parameter Symbol Min Max Unit Address setup before CS and RD low or CS and WR low Tias 5- ns Address hold time after CS and RD low or CS and WR low Tiah 5- ns Delay between RD then CS low or CS then RD low Ticdr 0 ∞ ns Data valid after CS and RD low (Note 3) Tidd -21 ns CS and RD low for read (Note 1) Tirpw DCLKP + 10 - ns Data hold time after CS or RD high Tidhr 5- ns Data high-Z after CS or RD high (Note 2) Tidis -22 ns CS or RD high to CS and RD low for next read (Note 1) Tird 2*DCLKP + 10 - ns CS or RD high to CS and WR low for next write (Note 1) Tirdtw 2*DCLKP + 10 - ns Delay between WR then CS low or CS then WR low Ticdw 0 ∞ ns Data setup before CS or WR high Tidsu 20 - ns CS and WR low for write (Note 1) Tiwpw DCLKP + 10 - ns Data hold after CS or WR high Tidhw 5- ns CS or WR high to CS and RD low for next read (Note 1) Tiwtrd 2*DCLKP + 10 - ns CS or WR high to CS and WR low for next write (Note 1) Tiwd 2*DCLKP + 10 - ns |
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