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AD9265BCPZRL7-80 데이터시트(PDF) 6 Page - Analog Devices |
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AD9265BCPZRL7-80 데이터시트(HTML) 6 Page - Analog Devices |
6 / 44 page AD9265 Rev. A | Page 6 of 44 Parameter1 Temp AD9265BCPZ-802 AD9265BCPZ-1052 AD9265BCPZ-1252 Unit Min Typ Max Min Typ Max Min Typ Max WORST OTHER (HARMONIC OR SPUR) Without Dither fIN = 2.4 MHz 25°C −106 −105 −101 dBc fIN = 70 MHz 25°C −106 −104 −103 dBc Full −97 −95 −92 dBc fIN = 140 MHz 25°C −104 −103 −104 dBc fIN = 200 MHz 25°C −102 −103 −100 dBc With On-Chip Dither fIN = 2.4 MHz 25°C −106 −105 −102 dBc fIN = 70 MHz 25°C −106 −105 −103 dBc Full −97 −99 −98 dBc fIN = 140 MHz 25°C −104 −103 −104 dBc fIN = 200 MHz 25°C −101 −101 −100 dBc TWO-TONE SFDR Without Dither fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS ) 25°C 93 90 95 dBc fIN = 169 MHz (−7 dBFS ), 172 MHz (−7 dBFS ) 25°C 80 78 79 dBc ANALOG INPUT BANDWIDTH 25°C 650 650 650 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 The suffix following the part number refers to the model found in the Ordering Guide section. DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 3. Parameter Temperature Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND AVDD V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full −100 +100 μA Low Level Input Current Full −100 +100 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ SYNC INPUT Logic Compliance CMOS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD V High Level Input Voltage Full 1.2 AVDD V Low Level Input Voltage Full AGND 0.6 V High Level Input Current Full −100 +100 μA Low Level Input Current Full −100 +100 μA Input Capacitance Full 1 pF Input Resistance Full 12 16 20 kΩ |
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