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LM3S8630-EQN20-A2T 데이터시트(PDF) 30 Page - Texas Instruments |
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LM3S8630-EQN20-A2T 데이터시트(HTML) 30 Page - Texas Instruments |
30 / 546 page – Master or slave operation – Programmable clock bit rate and prescale – Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep – Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces – Programmable data frame size from 4 to 16 bits – Internal loopback test mode for diagnostic/debug testing ■ I2C – Devices on the I2C bus can be designated as either a master or a slave • Supports both sending and receiving data as either a master or a slave • Supports simultaneous master and slave operation – Four I2C modes • Master transmit • Master receive • Slave transmit • Slave receive – Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps) – Master and slave interrupt generation • Master generates interrupts when a transmit or receive operation completes (or aborts due to an error) • Slave generates interrupts when data has been sent or requested by a master – Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode ■ Controller Area Network (CAN) – CAN protocol version 2.0 part A/B – Bit rates up to 1 Mbps – 32 message objects with individual identifier masks – Maskable interrupt – Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications – Programmable Loopback mode for self-test operation April 04, 2010 30 Texas Instruments-Production Data Architectural Overview |
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