전자부품 데이터시트 검색엔진 |
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LM3S8630-IQR50-A2T 데이터시트(PDF) 79 Page - Texas Instruments |
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LM3S8630-IQR50-A2T 데이터시트(HTML) 79 Page - Texas Instruments |
79 / 546 page Register 5: Interrupt Mask Control (IMC), offset 0x054 Central location for system control interrupt masks. Interrupt Mask Control (IMC) Base 0x400F.E000 Offset 0x054 Type R/W, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved BORIM reserved PLLLIM reserved RO R/W RO RO RO RO R/W RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 RO reserved 31:7 PLL Lock Interrupt Mask This bit specifies whether a PLL Lock interrupt is promoted to a controller interrupt. If set, an interrupt is generated if PLLLRIS in RIS is set; otherwise, an interrupt is not generated. 0 R/W PLLLIM 6 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 RO reserved 5:2 Brown-Out Reset Interrupt Mask This bit specifies whether a brown-out condition is promoted to a controller interrupt. If set, an interrupt is generated if BORRIS is set; otherwise, an interrupt is not generated. 0 R/W BORIM 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 RO reserved 0 79 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S8630 Microcontroller |
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