Complete 16-Bit

CCD/CIS Signal Processor

AD80066

Rev. A

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FEATURES

16-bit, 24 MSPS analog-to-digital converter (ADC)

4-channel operation up to 24 MHz (6 MHz/channel)

3-channel operation up to 24 MHz (8 MHz/channel)

Selectable input range: 3 V or 1.5 V peak-to-peak

Input clamp circuitry

Correlated double sampling

1×~6× programmable gain

±300 mV programmable offset

Internal voltage reference

Multiplexed byte-wide output

Optional single-byte output mode

3-wire serial digital interface

3 V/5 V digital I/O compatibility

Power dissipation: 490 mW at 24 MHz operation

Reduced power mode and sleep mode available

28-lead SSOP package

APPLICATIONS

Flatbed document scanners

Film scanners

Digital color copiers

Multifunction peripherals

GENERAL DESCRIPTION

The AD80066 is a complete analog signal processor for imaging

applications. It features a 4-channel architecture designed to sample

and condition the outputs of linear charged coupled device (CCD)

or contact image sensor (CIS) arrays. Each channel consists of

an input clamp, correlated double sampler (CDS), offset digital-

to-analog converter (DAC), and programmable gain amplifier

(PGA), multiplexed to a high performance 16-bit ADC. For

maximum flexibility, the AD80066 can be configured as a

4-channel, 3-channel, 2-channel, or 1-channel device.

The CDS amplifiers can be disabled for use with sensors that

do not require CDS, such as CIS and CMOS sensors.

The 16-bit digital output is multiplexed into an 8-bit output word,

which is accessed using two read cycles. There is an optional

single-byte output mode. The internal registers are programmed

through a 3-wire serial interface and enable adjustment of the

gain, offset, and operating mode. The AD80066 operates from a

5 V power supply, typically consumes 490 mW of power, and is

packaged in a 28-lead SSOP.

FUNCTIONAL BLOCK DIAGRAM

DOUT

(D[0:7])

SCLK

SLOAD

SDATA

ADCCLK

OFFSET

AVDD

AVSS

CML

AVDD

CAPT

CAPB

AD80066

DRVDD DRVSS

GAIN

REGISTERS

OFFSET

REGISTERS

4:1

MUX

16-BIT

ADC

CH. A

CH. B

CH. C

CH. D

8

16

CH. A

CH. B

CH. C

CH. D

6

9

PGA

PGA

PGA

CDS

CDS

CDS

AVSS

VIND

VINC

VINB

VINA

CDS

DIGITAL

CONTROL

INTERFACE

INPUT

CLAMP

BIAS

9-BIT

DAC

9-BIT

DAC

9-BIT

DAC

9-BIT

DAC

PGA

CONFIGURATION

REGISTER

MUX

REGISTER

CDSCLK2

CDSCLK1

BAND GAP

REFERENCE

16:8

MUX

Figure 1.