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ADD5203ACPZ-RL 데이터시트(PDF) 14 Page - Analog Devices |
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ADD5203ACPZ-RL 데이터시트(HTML) 14 Page - Analog Devices |
14 / 24 page ADD5203 Rev. 0 | Page 14 of 24 Slave Device Address As shown in Figure 23, the ADD5203 address consists of seven address bits plus one read/write (R/W) bit. If the device is in write mode, the LSB is set to 0 and the slave address byte is 0x58. If the device is in read mode, the LSB is set to 1 and the slave address byte is 0x59. tLOW tBUF tHD:DAT tSU:DAT tSU:STA tHD:STA tHIGH tR tF tSU:STO P S S P VIH VIL VIH VIL SCL SDA Figure 20. SMBus Interface SS RA A A W SLAVE ADDRESS COMMAND CODE SLAVE ADDRESS DATA BYTE P MASTER TO SLAVE SLAVE TO MASTER A Figure 21. Read Byte Protocol SW A A SLAVE ADDRESS COMMAND CODE DATA BYTE A P MASTER TO SLAVE SLAVE TO MASTER Figure 22. Write Byte Protocol R/W 0 0 1 1 0 1 0 Figure 23. Slave Address Definition |
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