전자부품 데이터시트 검색엔진 |
|
LM3S8630-IGZ20-A2 데이터시트(PDF) 64 Page - Texas Instruments |
|
LM3S8630-IGZ20-A2 데이터시트(HTML) 64 Page - Texas Instruments |
64 / 546 page The internal Power-On Reset (POR) circuit monitors the power supply voltage (VDD) and generates a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a threshold value (VTH). The microcontroller must be operating within the specified operating parameters when the on-chip power-on reset pulse is complete. The 3.3-V power supply to the microcontroller must reach 3.0 V within 10 msec of VDD crossing 2.0 V to guarantee proper operation. For applications that require the use of an external reset signal to hold the microcontroller in reset longer than the internal POR, the RST input may be used as discussed in “External RST Pin” on page 64. The Power-On Reset sequence is as follows: 1. The microcontroller waits for internal POR to go inactive. 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The internal POR is only active on the initial power-up of the microcontroller. The Power-On Reset timing is shown in Figure 20-6 on page 511. 6.1.2.4 External RST Pin Note: It is recommended that the trace for the RST signal must be kept as short as possible. Be sure to place any components connected to the RST signal as close to the microcontroller as possible. If the application only uses the internal POR circuit, the RST input must be connected to the power supply (VDD) through an optional pull-up resistor (0 to 100K Ω) as shown in Figure 6-1 on page 64. Figure 6-1. Basic RST Configuration PU RST Stellaris® R VDD RPU = 0 to 100 kΩ The external reset pin (RST) resets the microcontroller including the core and all the on-chip peripherals except the JTAG TAP controller (see “JTAG Interface” on page 51). The external reset sequence is as follows: 1. The external reset pin (RST) is asserted for the duration specified by TMIN and then de-asserted (see “Reset” on page 510). 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. To improve noise immunity and/or to delay reset at power up, the RST input may be connected to an RC network as shown in Figure 6-2 on page 65. April 04, 2010 64 Texas Instruments-Production Data System Control |
유사한 부품 번호 - LM3S8630-IGZ20-A2 |
|
유사한 설명 - LM3S8630-IGZ20-A2 |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |