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LM3S8630-EQC50-A2 데이터시트(PDF) 67 Page - Texas Instruments |
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LM3S8630-EQC50-A2 데이터시트(HTML) 67 Page - Texas Instruments |
67 / 546 page software a mechanism to adjust the regulated value, in small increments (VSTEP), over the range of 2.25 V to 2.75 V (inclusive)—or 2.5 V ± 10%. The adjustment is made by changing the value of the VADJ field in the LDO Power Control (LDOPCTL) register. Figure 6-4 on page 67 shows the power architecture. Note: On the printed circuit board, use the LDO output as the source of VDD25 input. In addition, the LDO requires decoupling capacitors. See “On-Chip Low Drop-Out (LDO) Regulator Characteristics” on page 504. Figure 6-4. Power Architecture I/O Buffers Analog circuits (ADC, analog comparators) Low-noise LDO Internal Logic and PLL GND GND GND GND GNDA GND GND GND GND VDD VDD VDD VDD VDDA VDDA VDD25 VDD25 VDD25 VDD25 LDO +3.3V Ethernet PHY GNDPHY GNDPHY GNDPHY GNDPHY VCCPHY VCCPHY VCCPHY VCCPHY GNDA VDD 67 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S8630 Microcontroller |
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