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LM3S8630-EQN50-A2 데이터시트(PDF) 29 Page - Texas Instruments

부품명 LM3S8630-EQN50-A2
상세설명  Stellaris짰 LM3S8630 Microcontroller
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
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LM3S8630-EQN50-A2 데이터시트(HTML) 29 Page - Texas Instruments

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– 16-bit PWM mode
Simple PWM mode with software-programmable output inversion of the PWM signal
■ ARM FiRM-compliant Watchdog Timer
– 32-bit down counter with a programmable load register
– Separate watchdog clock with an enable
– Programmable interrupt generation logic with interrupt masking
– Lock register protection from runaway software
– Reset generation logic with an enable/disable
– User-enabled stalling when the controller asserts the CPU Halt flag during debug
■ UART
– Two fully programmable 16C550-type UARTs with IrDA support
– Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
– Programmable baud-rate generator allowing speeds up to 3.125 Mbps
– Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
– Standard asynchronous communication bits for start, stop, and parity
– False-start bit detection
– Line-break generation and detection
– Fully programmable serial interface characteristics
5, 6, 7, or 8 data bits
Even, odd, stick, or no-parity bit generation/detection
1 or 2 stop bit generation
– IrDA serial-IR (SIR) encoder/decoder providing
Programmable use of IrDA Serial Infrared (SIR) or UART input/output
Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
Programmable internal clock generator enabling division of reference clock by 1 to 256
for low-power mode bit duration
■ Synchronous Serial Interface (SSI)
29
April 04, 2010
Texas Instruments-Production Data
Stellaris® LM3S8630 Microcontroller


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