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LM3S8630-EQN50-A2 데이터시트(PDF) 37 Page - Texas Instruments |
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LM3S8630-EQN50-A2 데이터시트(HTML) 37 Page - Texas Instruments |
37 / 546 page specifications and fully supports 10BASE-T and 100BASE-TX standards. In addition, the Ethernet Controller supports automatic MDI/MDI-X cross-over correction. 1.4.4 System Peripherals 1.4.4.1 Programmable GPIOs (see page 168) General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The Stellaris ® GPIO module is comprised of seven physical GPIO blocks, each corresponding to an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time Microcontrollers specification) and supports 10-31 programmable input/output pins. The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page 479 for the signals available to each GPIO pin). The GPIO module features programmable interrupt generation as either edge-triggered or level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in both read and write operations through address lines. Pins configured as digital inputs are Schmitt-triggered. 1.4.4.2 Four Programmable Timers (see page 209) Programmable timers can be used to count or time external events that drive the Timer input pins. The Stellaris ® General-Purpose Timer Module (GPTM) contains four GPTM blocks. Each GPTM block provides two 16-bit timers/counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event capture or Pulse Width Modulation (PWM) generation. 1.4.4.3 Watchdog Timer (see page 245) A watchdog timer can generate an interrupt or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. The Stellaris ® Watchdog Timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, and a locking register. The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. 1.4.5 Memory Peripherals The LM3S8630 controller offers both single-cycle SRAM and single-cycle Flash memory. 1.4.5.1 SRAM (see page 143) The LM3S8630 static random access memory (SRAM) controller supports 32 KB SRAM. The internal SRAM of the Stellaris ® devices is located at offset 0x0000.0000 of the device memory map. To reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. 37 April 04, 2010 Texas Instruments-Production Data Stellaris® LM3S8630 Microcontroller |
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