TDA9901_4

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 04 — 14 August 2008

9 of 18

NXP Semiconductors

TDA9901

Wideband differential digital controlled variable gain amplifier

[1]

Due to the behavior of the on-chip regulator a warm-up time of 1 minute (typical) is recommended for optimal performance.

[2]

[3]

In latching mode (pin TE LOW), the gain settling is latched at the rising edge of the clock input.

[4]

In transparent mode, the gain settling is directly controlled by the input data pattern.

[5]

The circuit may be used with a single TTL clock on CLK or CLKN. The unused clock pin has to be decoupled to ground with a 100 nF

capacitance.

[6]

There are four modes of operation for the clock inputs in non-TTL mode:

d) AC driving mode 4: when driving the CLK input directly and with any AC signal of minimum 0.1 V (p-p) and with a DC level of 2.5 V,

the gain change takes place on the rising edge of the clock signal. When driving the CLKN input with the same signal, gain change

via a 100 nF capacitor.

rise time

-

4.0

-

ns

fall time

-

4.0

-

ns

Digital inputs: pins TE, GRAY0, GRAY1 and GRAY2

LOW-level input voltage

0

-

0.8

V

HIGH-level input voltage

2.0

-

V

HIGH-level input current

−10

-

+10

µA

LOW-level input current

−10

-

+10

µA

input capacitance

-

-

3

pF

Clock inputs in TTL mode

LOW-level input voltage

[5] 0

-

0.8

V

HIGH-level input voltage

[5] 2.0

-

V

HIGH-level input current

15

-

80

µA

LOW-level input current

−40

-

−10

µA

input capacitance

-

-

2

pF

Clock inputs in differential mode

LOW-level input voltage

[6] 3.19

-

3.52

V

[6] 3.83

-

4.12

V

HIGH-level input current

15

-

80

µA

LOW-level input current

−40

-

−5

µA

input capacitance

-

-

2

pF

peak-to-peak differential

input voltage

DC voltage level = 2.5 V

0.1

-

2.0

V

Table 6.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit