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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TDA18271HD 데이터시트(PDF) 19 Page - NXP Semiconductors |
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TDA18271HD 데이터시트(HTML) 19 Page - NXP Semiconductors |
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19 / 70 page  TDA18271HD_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 19 May 2009 19 of 70 NXP Semiconductors TDA18271HD Silicon Tuner IC 9.3.12 Description of Main post-divider byte 9.3.13 Description of Main divider bytes 1, 2 and 3 9.3.14 Description of Extended bytes 1 to 23 Table 22. MPD - Main post-divider byte (subaddress 0Ch) bit description Legend: * power-on reset value. Bit Symbol Access Value Description 7 IF_NOTCH R/W 0* adds a DC notch in IF for better adjacent channels rejection; depends on standards; see Table 43 6 to 0 MAIN_POST_DIV[6:0] R/W 000 LO synthesizer post-divider; see Table 47 Table 23. MD1, MD2 and MD3 - Main divider bytes 1, 2 and 3 (address 0Dh, 0Eh and 0Fh) bit description Legend: * power-on reset value. Address Register Bit Symbol Access Value Description 0Dh MD1 7 - R/W 0* must be set to 0 6 to 0 MAIN_DIV[22:16] R/W 00h* LO synthesizer main divider bits 0Eh MD2 7 to 0 MAIN_DIV[15:8] R/W 00h* 0Fh MD3 7 to 0 MAIN_DIV[7:0] R/W 00h* Table 24. EB1 to EB23 - Extended bytes 1 to 23 (address 10h to 26h) bit description Legend: * power-on reset value. Address Register Bit Symbol Access Value Description 10h EB1 7 to 3 EB1[7:3] R 1 1111* extended byte 1 2 CALVCO_FORLON R determines VCO used during Normal mode operations 1* LO VCO is used 0 CAL VCO is used 1 AGC1_ALWAYS_ MASTERN R enables AGC1 normal operation whatever the tuner type (master or slave) 1* normal operation for the master; 6 dB fixed for the slave 0 normal operation for both the master and the slave 0 AGC1_FIRSTN R determines which AGC will be updated when detectors 1 and 2 are active 1* AGC1 and AGC2 both updated 0 AGC1 has priority on AGC2 11h EB2 7 to 0 EB2[7:0] R/W 0000 0001* extended byte 2 12h EB3 7 to 0 EB3[7:0] R/W 1000 0100* extended byte 3 |
유사한 부품 번호 - TDA18271HD_09 |
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