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MC68HC11EA9MFN2 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 52 Page - Freescale Semiconductor, Inc

๋ถ€ํ’ˆ๋ช… MC68HC11EA9MFN2
์ƒ์„ธ๋‚ด์šฉ  8-Bit Microcontrollers
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์ œ์กฐ์‚ฌ  FREESCALE [Freescale Semiconductor, Inc]
ํ™ˆํŽ˜์ด์ง€  http://www.freescale.com
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MC68HC11EA9MFN2 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 52 Page - Freescale Semiconductor, Inc

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MC68HC11EA9
52
MC68HC11EA9TS/D
ILIE โ€” Idle Line Interrupt Enable
0 = IDLE interrupts disabled
1 = SCI interrupt requested when IDLE status flag is set
TE โ€” Transmitter Enable
0 = Transmitter disabled
1 = Transmitter enabled
RE โ€” Receiver Enable
0 = Receiver disabled
1 = Receiver enabled
RWU โ€” Receiver Wake-Up Control
0 = Normal SCI receiver
1 = Wake-up enabled and receiver interrupts inhibited
SBK โ€” Send Break
0 = Break generator off
1 = Break codes generated as long as SBK = 1
TDRE โ€” Transmit Data Register Empty Flag
Set if transmit data can be written to SCDR; if TDRE = 0, transmit data register is busy. Cleared by
SCSR1 read with TDRE set, followed by SCDR write.
0 = Transmit data register contains data and is busy
1 = Transmit data register is empty and SCDR can be written
TC โ€” Transmit Complete Flag
Set if transmitter is idle (no data, preamble, or break transmission in progress). Cleared by SCSR1 read
with TC set, followed by SCDR write.
0 = Transmitter is busy
1 = Transmitter is idle and SCDR can be written
RDRF โ€” Receive Data Register Full Flag
Set if a received character is ready to be read from SCDR. Cleared by SCSR1 read with RDRF set,
followed by SCDR read.
IDLE โ€” Idle Line Detected Flag
Once cleared, IDLE is set again until the RxD line has been active and becomes idle once more. IDLE
flag is inhibited when RWU = 1. Set if the RxD line is idle. Cleared by SCSR1 read with IDLE set, fol-
lowed by SCDR read.
OR โ€” Overrun Error Flag
Set if a new character is received before a previously received character is read from SCDR. Cleared
by SCSR1 read with OR set, followed by SCDR read.
NF โ€” Noise Error Flag
Set if majority sample logic detects anything other than a unanimous decision. Cleared by SCSR1 read
with NF set, followed by SCDR read.
FE โ€” Framing Error
Set if a zero is detected where a stop bit was expected. Cleared by SCSR1 read with FE set, followed
by SCDR read.
SCSR1 โ€”
SCI Status Register 1
$102C
BIT 7
654321
BIT 0
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
RESET:
00000000
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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