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TMP320C6713BGLSA20EP 데이터시트(PDF) 9 Page - Texas Instruments

부품명 TMP320C6713BGLSA20EP
상세설명  FLOATING-POINT DIGITAL SIGNAL PROCESSORS
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홈페이지  http://www.ti.com
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SM320C6713-EP
SM320C6713B-EP
www.ti.com
SGUS049I – AUGUST 2003 – REVISED SEPTEMBER 2009
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
Check for Samples: SM320C6713-EP
1
FEATURES
1
2
• Highest Performance Floating Point Digital
• 32 Bit External Memory Interface (EMIF)
Signal Processors (DSPs): C6713/C6713B
– Glueless Interface to SRAM, EPROM, Flash,
– Eight 32 Bit Instructions/Cycle
SBSRAM, and SDRAM
– 32/64 Bit Data Word
– 512M Byte Total Addressable External
Memory Space
– 200 and 300 MHz Clock Rate
• Enhanced Direct Memory Access (EDMA)
– 5 Instruction Cycle Times
Controller (16 Independent Channels)
– 2400/1800 and 1600/1200 MIPS/MFLOPS
• 16 Bit Host Port Interface (HPI)
– Rich Peripheral Set, Optimized for Audio
• Two Multichannel Audio Serial Ports (McASPs)
– Highly Optimized C/C++ Compiler
– Two Independent Clock Zones Each
• Advanced Very Long Instruction Word (VLIW)
(One TX and One RX)
320C67x™ DSP Core
– Eight Serial Data Pins Per Port: Individually
– Eight Independent Functional Units:
Assignable to any of the Clock Zones
Two ALUs (Fixed Point)
– Wide Variety of I2S™ and Similar Bit Stream
Four ALUs (Floating Point and Fixed
Formats
Point)
– Integrated Digital Audio Interface Transmitter
Two Multipliers (Floating Point and Fixed
(DIT)
Point)
– Extensive Error Checking and Recovery
– Load Store Architecture With 32 32-Bit
• Two Inter-Integrated Circuit Bus (I2C™ Bus)
General Purpose Registers
Multi-Master and Slave Interfaces
– Instruction Packing Reduces Code Size
• Two Multichannel Buffered Serial Ports:
– All Instructions Conditional
– Serial Peripheral Interface (SPI)
• Instruction Set Features
– High Speed TDM Interface
– Native Instructions for IEEE 754
– AC97 Interface
– Byte Addressable (8/16/32 Bit Data)
• Two 32 Bit General Purpose Timers
– 8 Bit Overflow Protection
• Dedicated GPIO Module With 16 Pins (External
– Saturation; Bit-Field Extract, Set, Clear;
Interrupt Capable)
Bit-Counting; Normalization
• Flexible Phase Locked Loop (PLL) Based Clock
• L1/L2 Memory Architecture
Generator Module
– 4K Byte L1P Program Cache (Direct-Mapped)
• IEEE-1149.1 (JTAG)(1) Boundary-Scan
– 4K Byte L1D Data Cache (2-Way)
Compatible
– 256K Byte L2 Memory Total: 64K-Byte L2
• 272 Ball, Ball Grid Array Package (GDP)
Unified Cache/Mapped RAM, and 192K Byte
• 0.13
μm/6 Level Copper Metal Process
Additional L2 Mapped RAM
– CMOS Technology
• Device Configuration
• 3.3 V I/Os, 1.26 V Internal
– Boot Mode: HPI, 8/16/32 Bit ROM Boot
(1)
IEEE Standard 1149.1-1990 Standard-Test-Access Port and
– Endianness: Little Endian, Big Endian
Boundary Scan Architecture.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
320C67x, TMS320C67x, TMS320C6000, eXpressDSP, Code Composer Studio, DSP/BIOS, C6000, XDS, TMS320, PowerPAD, C62x, C67x
are trademarks of Texas Instruments.
Copyright © 2003–2009, Texas Instruments Incorporated
FEATURES
9
Submit Documentation Feedback
Product Folder Link(s): SM320C6713-EP


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