AUP

LVC

AUP

AUP

LVC

Static-Power Consumption

(

µA)

Dynamic-Power Consumption

(pF)

3.3-V

3.3-V

0%

20%

40%

60%

80%

100%

0%

20%

40%

60%

80%

100%

−0.5

0

0.5

1

1.5

2

2.5

3

3.5

0

5

10

15

20

25

30

35

40

45

Time − ns

† AUP1G08 data at C

Output

Input

Switching Characteristics

SN74AUP1G79

SCES592G – JULY 2004 – REVISED MAY 2010

www.ti.com

Figure 1. AUP – The Lowest-Power Family

Figure 2. Excellent Signal Integrity

This is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup time

requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock

triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the

hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the

package.

preventing damaging current backflow through the device when it is powered down.

ORDERABLE

TOP-SIDE

PART NUMBER

NanoStar – WCSP (DSBGA)

Reel of 3000

SN74AUP1G79YFPR

_ _ H W _

0.23-mm Large Bump – YFP (Pb-free)

NanoStar – WCSP (DSBGA)

Reel of 3000

SN74AUP1G79YZPR

_ _ H W _

0.23-mm Large Bump – YZP (Pb-free)

QFN – DRY

Reel of 5000

SN74AUP1G79DRYR

HW

uQFN – DSF

Reel of 5000

SN74AUP1G79DSFR

HW

–40°C to 85°C

Reel of 3000

SN74AUP1G79DBVR

SOT (SOT-23) – DBV

H79_

Reel of 250

SN74AUP1G79DBVT

Reel of 3000

SN74AUP1G79DCKR

SOT (SC-70) – DCK

HW_

Reel of 250

SN74AUP1G79DCKT

SOT (SOT-553) – DRL

Reel of 4000

SN74AUP1G79DRLR

HW_

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2)

Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3)

DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site.

YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).

FUNCTION TABLE

INPUTS

OUTPUT

Q

CLK

D

↑

H

H

↑

L

L

L or H

X

2

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Product Folder Link(s): SN74AUP1G79