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ADM1025ARQ-REEL 데이터시트(PDF) 4 Page - ON Semiconductor |
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ADM1025ARQ-REEL 데이터시트(HTML) 4 Page - ON Semiconductor |
4 / 21 page ADM1025/ADM1025A Preliminary Technical Data Rev. P5 | Page 4 of 21| www.onsemi.com Parameter Min Typ Max Unit Test Conditions/Comments SERIAL BUS TIMING Clock Frequency, fSCLK 400 kHz See Figure 2 Glitch Immunity, tSW 50 ns See Figure 2 Bus Free Time, tBUF 1.3 μs See Figure 2 Start Setup Time, tSU:STA 600 ns See Figure 2 Start Hold Time, tHD:STA 600 ns See Figure 2 Stop Condition Setup Time, tSU:STO 600 ns See Figure 2 SCL Low Time, tLOW 1.3 μs See Figure 2 SCL High Time, tHIGH 0.6 μs See Figure 2 SCL, SDA Rise Time, tR 300 ns See Figure 2 SCL, SDA Fall Time, tF 300 ns See Figure 2 Data Setup Time, tSU:DAT 100 ns See Figure 2 Data Hold Time, tHD:DAT 300 ns See Figure 2 1 All voltages are measured with respect to GND, unless otherwise specified. 2 Typicals are at TA = 25°C and represent most likely parametric norm. Shutdown current typ is measured with VCC = 3.3 V. 3 TUE (Total Unadjusted Error) includes Offset, Gain, and Linearity errors of the ADC, multiplexer, and on-chip input attenuators, including an external series input protection resistor value between zero and 1 kΩ. 4 Total monitoring cycle time is nominally 114.4 ms. Monitoring Cycle consists of 6 Voltage + 1 Internal Temperature + 1 External Temperature readings. 5 ADD is a three-state input that may be pulled high, low, or left open-circuit. 6 Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.2 V for a rising edge. |
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