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TDA19978B 데이터시트(PDF) 16 Page - NXP Semiconductors |
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TDA19978B 데이터시트(HTML) 16 Page - NXP Semiconductors |
16 / 38 page TDA19978B_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 10 May 2010 16 of 38 NXP Semiconductors TDA19978B Quad HDMI 1.3a receiver with digital processing 8.24.2 EDID memory shared over three HDMI inputs 9. I2C-bus protocol The TDA19978B is a slave I2C-bus device and the SCL pin is only an input pin. The timing and protocol for I2C-bus are standard. Bit A0 of the I2C-bus device address is externally selected by the A0 pin. The main device I2C-bus address is given in Table 7. 10. Limiting values (1) 253 bytes + 3 bytes input B + 3 bytes input C + 3 bytes input D + 1 byte address pointer (subPhys@): this indicates the address in each block where the data for inputs B, C and D will be copied. Fig 4. An example of an application with EDID shared over three HDMI inputs 001aai418 EDID: 253 B EXTERNAL EDID: 256 B or 512 B DVI or HDMI INPUT I2C-bus CPU FLASH(1) EDID CONTENT TDA19978B 3 B HDMI INPUT 3 B HDMI INPUT 3 B HDMI INPUT Table 7. I2C-bus slave address A6 A5 A4 A3 A2 A1 A0 R/W 10011 0 A0 0/1 Table 8. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDDx(3V3) supply voltage on all 3.3 V pins −0.5 +4.6 V VDDx(1V8) supply voltage on all 1.8 V pins −0.5 +2.5 V ΔV DD supply voltage difference −0.5 +0.5 V IO output current - 35 mA Tstg storage temperature −55 +150 °C Tamb ambient temperature 0 70 °C Tj junction temperature - 125 °C VESD electrostatic discharge voltage HBM −2000 +2000 V |
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