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CAT1232LPW-T2 데이터시트(PDF) 5 Page - ON Semiconductor |
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CAT1232LPW-T2 데이터시트(HTML) 5 Page - ON Semiconductor |
5 / 12 page CAT1232LP, CAT1832 © 2009 SCILLC. All rights reserved. 5 Doc. No. MD-3018 Rev. F Characteristics subject to change without notice APPLICATION INFORMATION SUPPLY VOLTAGE MONITOR Reset Signal Polarity and Output Stage Structure RESET ¯¯¯¯¯¯ is an active LOW signal. It is developed with an open drain driver in the CAT1232LP. A pull-up resistor is required, typical values are 10 kΩ to 50 kΩ. The CAT1832 uses a CMOS push-pull output stage for the RESET ¯¯¯¯¯¯. RESET is an active High signal developed by a CMOS push-pull output stage and is the logical opposite to RESET ¯¯¯¯¯¯. Trip Point Tolerance Selection The TOL input is used to select the VCC trip point threshold. This selection is made connecting the TOL input to ground or V CC. Connecting TOL to Ground makes the V CC trip threshold 4.62 V for the CAT1232LP and 2.88 V for the CAT1832. Connecting TOL to V CC makes the VCC trip threshold 4.37 V for the CAT1232LP and 2.55 V for the CAT1832. After VCC has risen above the trip point set by TOL, RESET and RESET ¯¯¯¯¯¯remain active for a minimum time period of 250 ms. On power-down, once V CC falls below the reset threshold the RESET outputs will remain active and are guaranteed valid down to a V CC level of 1.0 V. Trip Point Voltage (V) Tolerance Select Voltage Trip Point Tolerance Min Nominal Max CAT1232LP TOL = VCC 10 % 4.25 4.37 4.49 CAT1232LP TOL = GND 5 % 4.50 4.62 4.74 CAT1832 TOL = VCC 20 % 2.47 2.55 2.64 CAT1832 TOL = GND 10 % 2.80 2.88 2.97 Manual Reset Operation Push-button input, PBRST ¯¯¯¯¯¯, allows the user to issue reset signals. The pushbutton input is debounced and is pulled high through an internal 40 kΩ resistor. When PBRST ¯¯¯¯¯¯ is held low for the minimum time of 20 ms, both resets become active and remain active for a minimum time period of 250 ms after PBRST returns high. No external pull-up resistor is required, since PBRST ¯¯¯¯¯¯ is pulled high by an internal 40 kΩ resistor. PBRST ¯¯¯¯¯¯ can be driven from a TTL or CMOS logic line or short-ed to ground with a mechanical switch. Figure 1. Timing Diagram: Power Up Figure 2. Timing Diagram: Power Down VCCTP(MAX) VCCTP VCCTP(MIN) VCC RESET RESET tR tRPU VOH VOL VCCTP(MAX) VCCTP VCCTP(MIN) VCC RESET RESET tF VOH VOL tRPD |
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