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SN74HC273DBRE4 데이터시트(PDF) 2 Page - Texas Instruments |
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SN74HC273DBRE4 데이터시트(HTML) 2 Page - Texas Instruments |
2 / 20 page SN54HC273, SN74HC273 OCTAL DTYPE FLIPFLOPS WITH CLEAR SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. FUNCTION TABLE (each flip-flop) INPUTS OUTPUT CLR CLK D OUTPUT Q L X X L H ↑ HH H ↑ LL H L X Q0 logic diagram (positive logic) CLK 1D 3 1D C1 R 1Q 2 2D 4 1D C1 R 2Q 5 3D 7 1D C1 R 3Q 6 4D 8 1D C1 R 4Q 9 5D 13 1D C1 R 5Q 12 6D 14 1D C1 R 6Q 15 7D 17 1D C1 R 7Q 16 8D 18 1D C1 R 8Q 19 CLR 11 1 logic diagram, each flip-flop (positive logic) CLK(I) R Q C C D C C C C C C TG TG TG TG C C |
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