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SN74AUP1G98DCKTG4 데이터시트(PDF) 3 Page - Texas Instruments |
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3 / 26 page 3 1 6 C B A 4 Y 1 2 3 6 5 4 B Y C VCC B A C Y A GND 1 2 3 6 5 4 A Y C VCC C Y A GND SN74AUP1G98 www.ti.com SCES506H – NOVEMBER 2003 – REVISED MAY 2010 LOGIC DIAGRAM (POSITIVE LOGIC) Table 1. FUNCTION SELECTION TABLE LOGIC FUNCTION FIGURE NO. 2-to-1 data selector with inverted output Figure 3 2-input NAND gate Figure 4 2-input NOR gate with one inverted input Figure 5 2-input AND gate with one inverted input Figure 5 2-input NAND gate with one inverted input Figure 6 2-input OR gate with one inverted input Figure 6 2-input NOR gate Figure 7 Noninverted buffer Figure 8 Inverter Figure 9 LOGIC CONFIGURATIONS Figure 3. 2-to-1 Data Selector With Inverted Output When C is L, Y = B When C is H, Y = A Figure 4. 2-Input NAND Gate Copyright © 2003–2010, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): SN74AUP1G98 |
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