전자부품 데이터시트 검색엔진 |
|
LM3S8730-EBZ50-A2T 데이터시트(PDF) 95 Page - Texas Instruments |
|
LM3S8730-EBZ50-A2T 데이터시트(HTML) 95 Page - Texas Instruments |
95 / 551 page Register 14: Device Capabilities 1 (DC1), offset 0x010 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: CANs, PWM, ADC, Watchdog timer, Hibernation module, and debug capabilities. This register also indicates the maximum clock frequency and maximum ADC sample rate. The format of this register is consistent with the RCGC0, SCGC0, and DCGC0 clock control registers and the SRCR0 software reset control register. Device Capabilities 1 (DC1) Base 0x400F.E000 Offset 0x010 Type RO, reset 0x0100.30DF 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved CAN0 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 JTAG SWD SWO WDT PLL reserved HIB MPU reserved MINSYSDIV RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 1 1 1 1 1 0 1 1 0 0 0 0 1 1 0 0 Reset Description Reset Type Name Bit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 RO reserved 31:25 CAN Module 0 Present When set, indicates that CAN unit 0 is present. 1 RO CAN0 24 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 RO reserved 23:16 System Clock Divider Minimum 4-bit divider value for system clock. The reset value is hardware-dependent. See the RCC register for how to change the system clock divisor using the SYSDIV bit. Description Value Specifies a 50-MHz CPU clock with a PLL divider of 4. 0x3 0x3 RO MINSYSDIV 15:12 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 RO reserved 11:8 MPU Present When set, indicates that the Cortex-M3 Memory Protection Unit (MPU) module is present. See the ARM Cortex-M3 Technical Reference Manual for details on the MPU. 1 RO MPU 7 Hibernation Module Present When set, indicates that the Hibernation module is present. 1 RO HIB 6 95 June 22, 2010 Texas Instruments-Production Data Stellaris® LM3S8730 Microcontroller |
유사한 부품 번호 - LM3S8730-EBZ50-A2T |
|
유사한 설명 - LM3S8730-EBZ50-A2T |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |