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LM3S8730-EBZ80-A2T 데이터시트(PDF) 84 Page - Texas Instruments |
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LM3S8730-EBZ80-A2T 데이터시트(HTML) 84 Page - Texas Instruments |
84 / 551 page Register 7: Reset Cause (RESC), offset 0x05C This register is set with the reset cause after reset. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an power-on reset is the cause, in which case, all bits other than POR in the RESC register are cleared. Reset Cause (RESC) Base 0x400F.E000 Offset 0x05C Type R/W, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 EXT POR BOR WDT SW reserved R/W R/W R/W R/W R/W RO RO RO RO RO RO RO RO RO RO RO Type - - - - - 0 0 0 0 0 0 0 0 0 0 0 Reset Description Reset Type Name Bit/Field Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 RO reserved 31:5 Software Reset When set, indicates a software reset is the cause of the reset event. - R/W SW 4 Watchdog Timer Reset When set, indicates a watchdog reset is the cause of the reset event. - R/W WDT 3 Brown-Out Reset When set, indicates a brown-out reset is the cause of the reset event. - R/W BOR 2 Power-On Reset When set, indicates a power-on reset is the cause of the reset event. - R/W POR 1 External Reset When set, indicates an external reset (RST assertion) is the cause of the reset event. - R/W EXT 0 June 22, 2010 84 Texas Instruments-Production Data System Control |
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