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LM3S8730-EQC50-A2 데이터시트(PDF) 58 Page - Texas Instruments

부품명 LM3S8730-EQC50-A2
상세설명  Stellaris짰 LM3S8730 Microcontroller
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LM3S8730-EQC50-A2 데이터시트(HTML) 58 Page - Texas Instruments

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2.
Send the 16-bit JTAG-to-SWD switch sequence, 16'hE79E.
3.
Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was
already in SWD mode, before sending the switch sequence, the SWD goes into the line reset
state.
SWD-to-JTAG Switching
To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the
external debug hardware must send a switch sequence to the device. The 16-bit switch sequence
for switching to JTAG mode is defined as b1110011100111100, transmitted LSB first. This can also
be represented as 16'hE73C when transmitted LSB first. The complete switch sequence should
consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1.
Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and
SWD are in their reset/idle states.
2.
Send the 16-bit SWD-to-JTAG switch sequence, 16'hE73C.
3.
Send at least 5 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was
already in JTAG mode, before sending the switch sequence, the JTAG goes into the Test Logic
Reset state.
5.3
Initialization and Configuration
After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for
JTAG communication. No user-defined initialization or configuration is needed. However, if the user
application changes these pins to their GPIO function, they must be configured back to their JTAG
functionality before JTAG communication can be restored. This is done by enabling the five JTAG
pins (PB7 and PC[3:0]) for their alternate function using the GPIOAFSEL register. In addition to
enabling the alternate functions, any other changes to the GPIO pad configurations on the five JTAG
pins (PB7 andPC[3:0]) should be reverted to their default settings.
5.4
Register Descriptions
There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The
registers within the JTAG controller are all accessed serially through the TAP Controller. The registers
can be broken down into two main categories: Instruction Registers and Data Registers.
5.4.1
Instruction Register (IR)
The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain connected between the JTAG
TDI
and TDO pins with a parallel load register. When the TAP Controller is placed in the correct
states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the
chain and updated, they are interpreted as the current instruction. The decode of the Instruction
Register bits is shown in Table 5-2 on page 58. A detailed explanation of each instruction, along
with its associated Data Register, follows.
Table 5-2. JTAG Instruction Register Commands
Description
Instruction
IR[3:0]
Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction onto the pads.
EXTEST
0000
Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction into the controller.
INTEST
0001
June 22, 2010
58
Texas Instruments-Production Data
JTAG Interface


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