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CDCE937PWR 데이터시트(PDF) 2 Page - Texas Instruments

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부품명 CDCE937PWR
상세설명  Programmable 3-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V and 3.3-V LVCMOS Outputs
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
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CDCE937
CDCEL937
SLAS564F – AUGUST 2007 – REVISED MARCH 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION
The CDCE937 and CDCEL937 are modular PLL-based low cost, high-performance, programmable clock
synthesizers, multipliers and dividers. They generate up to 7 output clocks from a single input frequency. Each
output can be programmed in-system for any clock frequency up to 230 MHz, using up to three independent
configurable PLLs.
The CDCx937 has separate output supply pins, VDDOUT, which is 1.8 V for CDCEL937 and to 2.5 V to 3.3 V for
CDCE937.
The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load
capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF.
Additionally, an on-chip VCXO is selectable which allows synchronization of the output frequency to an external
control signal, that is, PWM signal.
The deep M/N divider ratio allows the generation of zero ppm audio/video, networking (WLAN, BlueTooth,
Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency such as
27 MHz.
All PLLs supports SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking which
is a common technique to reduce electro-magnetic interference (EMI).
Based on the PLL frequency and the divider settings, the internal loop filter components are automatically
adjusted to achieve high stability and optimized jitter transfer characteristic of each PLL.
The device supports non-volatile EEPROM programming for ease-customized application. It is preset to a factory
default configuration (see the Default Device Configuration section). It can be reprogrammed to a different
application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings
are programmable through SDA/SCL bus, a 2-wire serial interface.
Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including
frequency selection changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing
between low level or 3-state for output-disable function.
The CDCx937 operates in 1.8 V environment. It is characterized for operation from –40°C to 85°C.
Terminal Functions for CDCE937, CDCEL937
NAME
PIN TSSOP24
TYPE
DESCRIPTION
Y1, Y2, ...
17, 15, 14, 7,
O
LVCMOS outputs
Y7
8, 12, 11
Xin/CLK
1
I
Crystal Oscillator Input or LVCMOS Clock Input (selectable via SDA/SCL bus)
Xout
20
O
Crystal Oscillator Output (leave open or pull-up (~500k) when not used)
VCtrl
4
I
VCXO Control Voltage (leave open or pull-up (~500k) when not used)
VDD
3
Power
1.8V Power Supply for the device
CDCEL937: 1.8V Supply for all Outputs
Vddout
6, 10, 13
Power
CDCE937: 3.3V or 2.5V Supply for all Outputs
GND
5, 9, 16
Ground
Ground
S0
2
I
User Programmable Control Input S0; LVCMOS inputs; Internal Pull-up 500k
SDA: Bi-Directional Serial Data Input/Output (default configuration). LVCMOS; Internal Pull-up
SDA/S1
19
I/O or I
500k; or
S1: User Programmable Control Input; LVCMOS inputs; Internal Pull-up 500k
SCL: Serial Clock Input(default configuration), LVCMOS; Internal Pull-up 500k; or
SCL/S2
18
I
S2: User Programmable Control Input; LVCMOS inputs; Internal Pull-up 500k
2
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Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): CDCE937 CDCEL937


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