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TS3A4742DCNR 데이터시트(PDF) 8 Page - Texas Instruments |
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TS3A4742DCNR 데이터시트(HTML) 8 Page - Texas Instruments |
8 / 17 page www.ti.com APPLICATION INFORMATION Logic Inputs Analog Signal Levels Layout TS3A4741,, TS3A4742 0.9- Ω LOW-VOLTAGE SINGLE-SUPPLY DUAL SPST ANALOG SWITCHES SCDS228D – AUGUST 2006 – REVISED JANUARY 2008 Proper power-supply sequencing is recommended for all CMOS devices. Do not exceed the absolute maximum ratings, because stresses beyond the listed ratings can cause permanent damage to the device. Always sequence V+ on first, followed by NO, NC, or COM. Although it is not required, power-supply bypassing improves noise margin and prevents switching noise propagation from the V+ supply to other components. A 0.1-µF capacitor, connected from V+ to GND, is adequate for most applications. The TS3A4741 logic inputs can be driven up to 3.6 V, regardless of the supply voltage. For example, with a 1.8-V supply, IN may be driven low to GND and high to 3.6 V. Driving IN rail to rail minimizes power consumption. Analog signals that range over the entire supply voltage (V+ to GND) can be passed with very little change in ron (see Typical Operating Characteristics). The switches are bidirectional, so the NO, NC, and COM pins can be used as either inputs or outputs. High-speed switches require proper layout and design procedures for optimum performance. Reduce stray inductance and capacitance by keeping traces short and wide. Ensure that bypass capacitors are as close to the device as possible. Use large ground planes where possible. 8 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): TS3A4741 TS3A4742 |
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