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LM3S8630-IQC50-A2 데이터시트(PDF) 86 Page - Texas Instruments

부품명 LM3S8630-IQC50-A2
상세설명  Stellaris짰 LM3S8630 Microcontroller
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홈페이지  http://www.ti.com
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LM3S8630-IQC50-A2 데이터시트(HTML) 86 Page - Texas Instruments

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Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
21:14
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value of 1 powers
down the PLL.
1
R/W
PWRDN
13
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
RO
reserved
12
PLL Bypass
Chooses whether the system clock is derived from the PLL output or
the OSC source. If set, the clock that drives the system is the OSC
source. Otherwise, the clock that drives the system is the PLL output
clock divided by the system divider.
See Table 6-2 on page 71 for programming guidelines.
1
R/W
BYPASS
11
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
10
Crystal Value
This field specifies the crystal value attached to the main oscillator. The
encoding for this field is provided below. Depending on the crystal used,
the PLL frequency may not be exactly 400 MHz (see Table
20-9 on page 511 for more information).
Crystal Frequency (MHz) Using
the PLL
Crystal Frequency (MHz) Not
Using the PLL
Value
reserved
1.000
0x0
reserved
1.8432
0x1
reserved
2.000
0x2
reserved
2.4576
0x3
3.579545 MHz
0x4
3.6864 MHz
0x5
4 MHz
0x6
4.096 MHz
0x7
4.9152 MHz
0x8
5 MHz
0x9
5.12 MHz
0xA
6 MHz (reset value)
0xB
6.144 MHz
0xC
7.3728 MHz
0xD
8 MHz
0xE
8.192 MHz
0xF
0xB
R/W
XTAL
9:6
June 22, 2010
86
Texas Instruments-Production Data
System Control


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