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LM3S8630-IQC50-A2 데이터시트(PDF) 20 Page - Texas Instruments |
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LM3S8630-IQC50-A2 데이터시트(HTML) 20 Page - Texas Instruments |
20 / 550 page Table 1. Revision History (continued) Description Revision Date ■ Corrected values for DSOSCSRC bit field in Deep Sleep Clock Configuration (DSLPCLKCFG) register. ■ The FMA value for the FMPRE3 register was incorrect in the Flash Resident Registers table in the Internal Memory chapter. The correct value is 0x0000.0006. ■ In the CAN chapter, major improvements were made including a rewrite of the conceptual information and the addition of new figures to clarify how to use the Controller Area Network (CAN) module. ■ In the Ethernet chapter, major improvements were made including a rewrite of the conceptual information and the addition of new figures to clarify how to use the Ethernet Controller interface. 4149 October 2008 ■ Added note on clearing interrupts to Interrupts chapter. ■ Added Power Architecture diagram to System Control chapter. ■ Additional minor data sheet clarifications and corrections. 3447 August 2008 ■ Corrected resistor value in ERBIAS signal description. ■ Additional minor data sheet clarifications and corrections. 3108 July 2008 ■ As noted in the PCN, three of the nine Ethernet LED configuration options are no longer supported: TX Activity (0x2), RX Activity (0x3), and Collision (0x4). These values for the LED0 and LED1 bit fields in the MR23 register are now marked as reserved. ■ As noted in the PCN, the option to provide VDD25 power from external sources was removed. Use the LDO output as the source of VDD25 input. ■ As noted in the PCN, pin 41 (ball K3 on the BGA package) was renamed from GNDPHY to ERBIAS. A 12.4-kΩ resistor should be connected between ERBIAS and ground to accommodate future device revisions (see “Functional Description” on page 434). ■ Additional minor data sheet clarifications and corrections. 2972 May 2008 2881 April 2008 ■ The ΘJA value was changed from 55.3 to 34 in the "Thermal Characteristics" table in the Operating Characteristics chapter. ■ Bit 31 of the DC3 register was incorrectly described in prior versions of the data sheet. A reset of 1 indicates that an even CCP pin is present and can be used as a 32-KHz input clock. ■ Values for IDD_HIBERNATE were added to the "Detailed Power Specifications" table in the "Electrical Characteristics" chapter. ■ The "Hibernation Module DC Electricals" table was added to the "Electrical Characteristics" chapter. ■ The TVDDRISE parameter in the "Reset Characteristics" table in the "Electrical Characteristics" chapter was changed from a max of 100 to 250. ■ The maximum value on Core supply voltage (VDD25) in the "Maximum Ratings" table in the "Electrical Characteristics" chapter was changed from 4 to 3. ■ The operational frequency of the internal 30-kHz oscillator clock source is 30 kHz ± 50% (prior data sheets incorrectly noted it as 30 kHz ± 30%). ■ A value of 0x3 in bits 5:4 of the MISC register (OSCSRC) indicates the 30-KHz internal oscillator is the input source for the oscillator. Prior data sheets incorrectly noted 0x3 as a reserved value. ■ The reset for bits 6:4 of the RCC2 register (OSCSRC2) is 0x1 (IOSC). Prior data sheets incorrectly noted the reset was 0x0 (MOSC). ■ Two figures on clock source were added to the "Hibernation Module": June 22, 2010 20 Texas Instruments-Production Data Revision History |
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