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MC14555B 데이터시트(PDF) 3 Page - Motorola, Inc |
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MC14555B 데이터시트(HTML) 3 Page - Motorola, Inc |
3 / 5 page MOTOROLA CMOS LOGIC DATA 3 MC14555B MC14556B SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C) Characteristic Symbol VDD Min Typ # Max Unit Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL 5.0 10 15 — — — 100 50 40 200 100 80 ns Propagation Delay Time — A, B to Output tPLH, tPHL = (1.7 ns/pF) CL + 135 ns tPLH, tPHL = (0.66 ns/pF) CL + 62 ns tPLH, tPHL = (0.5 ns/pF) CL + 45 ns tPLH, tPHL 5.0 10 15 — — — 220 95 70 440 190 140 ns Propagation Delay Time — E to Output tPLH, tPHL = (1.7 ns/pF) CL + 115 ns tPLH, tPHL = (0.66 ns/pF) CL + 52 ns tPLH, tPHL = (0.5 ns/pF) CL + 40 ns tPLH, tPHL 5.0 10 15 — — — 200 85 65 400 170 130 ns * The formulas given are for the typical characteristics only at 25 _C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. Figure 1. Dynamic Power Dissipation Signal Waveforms Figure 2. Dynamic Signal Waveforms All 8 outputs connect to respective CL loads. f in respect to a system clock. INPUT E LOW 20 ns 20 ns 90% 50% 10% 2f 1 VDD VSS VDD VSS VOH VOL A INPUTS (50% DUTY CYCLE) B INPUTS (50% DUTY CYCLE) OUTPUT Q1 20 ns 20 ns VDD VSS VOH VOL VOH VOL 90% 50% 10% 90% 50% 10% 90% 50% 10% tPLH tTLH tPHL tPHL tTHL tPLH tTLH tTHL INPUT A HIGH, INPUT E LOW INPUT B OUTPUT Q3 MC14556B OUTPUT Q3 MC14555B LOGIC DIAGRAM (1/2 of Dual) * Eliminated for MC14555B * * * * Q0 Q1 Q2 Q3 E B A |
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