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S5N8950 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 6 Page - Samsung semiconductor

๋ถ€ํ’ˆ๋ช… S5N8950
์ƒ์„ธ๋‚ด์šฉ  G.dmt ADSL Transceiver for CO and CPE
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์ œ์กฐ์‚ฌ  SAMSUNG [Samsung semiconductor]
ํ™ˆํŽ˜์ด์ง€  http://www.samsung.com/Products/Semiconductor
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S5N8950 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 6 Page - Samsung semiconductor

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S5N8950
G.dmt ADSL Transceiver for CO and CPE
CONFIDENTIAL
Preliminary Information ( Rev 1.2 )
Interface
Type
Mnemonic
Type
Driver
Function
U_TX_ADDR[4:0]
I
PHTICD
Utopia Tx Address
U_TX_DATA[7:0]
I
PHTICD
Utopia Tx Data
U_TX_ENB
I
PHTICD
Utopia Tx Enable
U_TX_SOC
I
PHTICD
Utopia Tx Start of Cell
U_TX_CLK
I
PHTICD
Utopia Tx Clock. 25 MHz
U_TX_CLAV
OZ
PHTOT4
Utopia Tx Cell Available
U_RX_ADDR[4:0]
I
PHTICD
Utopia Rx Address[4:0]
U_RX_DATA[7:0]
OZ
PHTOT4
Utopia Rx Data[7:0]
U_RX_ENB
I
PHTICD
Utopia Rx Enable
U_RX_SOC
OZ
PHTOT4
Utopia Rx Start of Cell
U_RX_CLK
I
PHTICD
Utopia Rx Clock. 25 MHz
U_RX_CLAV
OZ
PHTOT4
Utopia Rx Cell Available
ATM
interface
S1_TX_DAV
O
PHOB4
Serial Tx data valid signal in the 1-st STM
S1_TX_CLK
O
PHOB4
Serial Tx clock in the 1-st STM
S1_TX_DATA
I
PHTICD
Serial Tx data in the 1-st STM
S1_RX_DAV
O
PHOB4
Serial Rx data valid signal in the 1-st STM
S1_RX_CLK
O
PHOB4
Serial Rx clock in the 1-st STM
S1_RX_DATA
O
PHOB4
Serial Rx data in the 1-st STM
S2_TX_DAV
O
PHOB4
Serial Tx data valid signal in the 2-nd STM
S2_TX_CLK
O
PHOB4
Serial Tx clock in the 2-nd STM
S2_TX_DATA
I
PHTICD
Serial Tx data in the 2-nd STM
S2_RX_DAV
O
PHOB4
Serial Rx data valid in the 2-nd STM
S2_RX_CLK
O
PHOB4
Serial Rx clock in the 2-nd STM
S2_RX_DATA
O
PHOB4
Serial Rx data in the 2-nd STM
STM
interface
H_SEL
I
PHTICD
Host type : [0]=Motorola / [1]= Intel
H_ADDR[9:0]
I
PHTICD
Host address bus
H_DATA[7:0]
B
PHTBCDT6SM
Host data bus
H_CSN
I
PHTICD
Chip selection
Motorola
Not used.
H_RDN
I
PHTICD
Intel
Read enable ( active low )
Motorola
[0]=write enable / [1]=read enable
H_WRN
I
PHTICD
Intel
Write Enable ( active low )
Motorola
Host CPU DTACK ( active low )
H_READY
OZ
PHTOT4
Intel
Host CPU Ready (active high )
Motorola
Interrupt IRQ ( active low )
H_INT
O
PHOB4
Intel
Interrupt INT ( active high )
H_WAKEUP
O
PHOB4
Host Wakeup
Host
Interface


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