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TPS59116RGER 데이터시트(PDF) 4 Page - Texas Instruments

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부품명 TPS59116RGER
상세설명  Complete DDR, DDR2 and DDR3 Memory Power Solution Synchronous Buck Controller 3-A LDO, Buffered Reference for Embedded Computing Systems
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI - Texas Instruments

TPS59116RGER 데이터시트(HTML) 4 Page - Texas Instruments

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TI Information — Selective Disclosure
TPS59116
SLUSA57 – AUGUST 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VV5IN = VV5FILT = 5 V, VLDOIN is connected to VDDQ output (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VTT OUTPUT (continued)
VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVTTSNS =
3.0
3.8
6.0
1.19 V, PGOOD = HI
IVTTTOCLSRC
Source current limit, VTT
VVLDOIN = VVDDQSNS = 2.5 V, VVTT = 0 V
1.5
2.2
3.0
A
VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVTTSNS =
3.0
3.6
6.0
1.31 V, PGOOD = HI
IVTTTOCLSNK
Sink current limit, VTT
VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVDDQ
1.5
2.2
3.0
IVTTLK
Leakage current, VTT
VS3 = 0 V, VS5 = 5 V, VVTT = VVDDQSNS /2
-10
10
IVTTBIAS
Input bias current, VTTSNS
VS3 = 5 V, VVTTSNS = VVDDQSNS /2
-1
-0.1
1
mA
IVTTSNSLK
Leakage current, VTTSNS
VS3 = 0 V, VS5 = 5 V, VVTT = VVDDQSNS /2
-1
1
TA = 25°C, VS3 = VS5 = VVDDQSNS = 0 V,
IVTTDisch
Discharge current, VTT
10
17
mA
VVTT = 0.5 V
VDDQ OUTPUT
TA = 25°C, VVDDQSET = 0 V, No load
2.465
2.500
2.535
0°C
≤ TA ≤ 85°C, VVDDQSET = 0 V, No load
(1)
2.457
2.500
2.543
-40°C
≤ TA ≤ 85°C, VVDDQSET = 0 V, No load
(1)
2.440
2.500
2.550
TA = 25°C, VVDDQSET = 5 V, No load
(1)
1.776
1.800
1.824
VVDDQ
Output voltage, VDDQ
V
0°C
≤ TA ≤ 85°C, VVDDQSET = 5V, No load
(1)
1.769
1.800
1.831
-40°C
≤ TA ≤ 85°C, VVDDQSET = 5V, No load
(1)
1.764
1.800
1.836
-40°C
≤ TA ≤ 85°C, Adjustable mode, No
0.75
3.0
load(1)
TA = 25°C, Adjustable mode
742.5
750.0
757.5
VVDDQSET
VDDQSET regulation voltage 0°C
≤ TA ≤ 85°C, Adjustable mode
740.2
750.0
759.8
mV
-40°C
≤ TA ≤ 85°C, Adjustable mode
738.0
750.0
762.0
VVDDQSET = 0 V
215
RVDDQSNS
Input impedance, VDDQSNS VVDDQSET = 5 V
180
k
Adjustable mode
460
VVDDQSET = 0.78 V, COMP = Open
-0.04
IVDDQSET
Input current, VDDQSET
mA
VVDDQSET = 0.78 V, COMP = 5 V
-0.06
VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V,
IVDDQDisch
Discharge current, VDDQ
10
40
VMODE = 0 V
mA
VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V,
IVLDOINDisch
Discharge current, VLDOIN
700
VMODE = 0.5 V
TRANSCONDUCTANCE AMPLIFIER
gM
Gain
TA = 25°C
240
300
360
mS
COMP maximum sink
VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V,
ICOMPSNK
13
current
VVDDQSNS = 2.7 V, VCOMP = 1.28 V
mA
COMP maximum source
VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V,
ICOMPSRC
-13
current
VVDDQSNS = 2.3 V, VCOMP = 1.28 V
VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V,
VCOMPHI
COMP high clamp voltage
1.31
1.34
1.37
VVDDQSNS = 2.3 V, VCS = 0 V
V
VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V,
VCOMPLO
COMP low clamp voltage
1.18
1.21
1.24
VVDDQSNS = 2.7 V, VCS = 0 V
DUTY CONTROL
tON
Operating on-time
VIN = 12 V, VVDDQSET = 0 V
520
tON0
Startup on-time
VIN = 12 V, VVDDQSNS = 0 V
125
ns
tON(min)
Minimum on-time
TA = 25°C
(1)
100
tOFF(min)
Minimum off-time
TA = 25°C
(1)
350
(1)
Ensured by design. Not production tested.
4
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