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ISL12024IVZ 데이터시트(PDF) 5 Page - Intersil Corporation |
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ISL12024IVZ 데이터시트(HTML) 5 Page - Intersil Corporation |
5 / 25 page 5 FN6370.1 October 18, 2006 Timing Diagrams Bus Timing Write Cycle Timing tDH Output Data Hold Time From SCL falling edge crossing 30% of VDD, until SDA enters the 30% to 70% of VDD window. 0ns Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip. 10 400 pF Cpin SDA, and SCL Pin Capacitance 10 pF tWC Non-volatile Write Cycle Time 12 20 ms NOTES: 3. IRQ/FOUT Inactive. 4. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz 5. VDD > VBAT +VBATHYS 6. Bit BSW = 0 (Standard Mode), VBAT ≥1.8V 7. Specified at +25°C. 8. In order to ensure proper timekeeping, the VDD SR- specification must be followed. 9. Parameter is not 100% tested. 10. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user (it is the time from valid STOP condition at the end of Write sequence of a serial interface Write operation) to the end of the self-timed internal non-volatile write cycle. AC Electrical Specifications (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS tSU:STO tDH tHIGH tSU:STA tHD:STA tHD:DAT tSU:DAT SCL SDA (INPUT TIMING) SDA (OUTPUT TIMING) tF tLOW tBUF tAA tR tHD:STO SCL SDA tWC 8TH BIT OF LAST BYTE ACK STOP CONDITION START CONDITION ISL12024 |
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